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RM0008
Inter-integrated circuit (I 2 C) interface
Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
●
●
An acknowledge pulse if the ACK bit is set
The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the next data
reception, the BTF bit is set and the interface waits until BTF is cleared by a read from
I2C_SR1 followed by a read from the I2C_DR register, stretching SCL low (see Figure 234
Transfer sequencing).
Figure 234. Transfer sequence diagram for slave receiver
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets,
●
The STOPF bit and generates an interrupt if the ITEVFEN bit is set.
Then the interface waits for a read of the SR1 register followed by a write to the CR1 register
(see Figure 234 Transfer sequencing EV4).
Doc ID 13902 Rev 9
629/995
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